VSD - RISCV : Instruction Set Architecture (ISA) - Part 1b

Overview

This course is in continuation with my previous course "VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a" which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.

All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course atleast 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture - An important one needed in today's fast changing computing world.

Understand RISC-V architecture in greater detail, and, as per speculations and other articles, this is the architecture which you will find in almost 1 trillion mobile devices, this course will make you look at new future
Learn how computers and processors does basic calculations

Objective

Introduction
Overflow conditions for signed addition and subtraction
- Signed addition and overflow condition for 4-bit word
- Derived overflow conditions for signed addition
- RISC-V overflow checking program for signed addition
- Signed subtraction using addition hardware for 4-bit word
- Overflow condition and conclusion for signed subtraction
RV64M - Multiply extension instruction set
- Multiplication algorithm for 4-bit integers
- 'mulh' and 'mul' commands to store 128-bit product
- Class-room division method and initialize registers
- Division algorithm initiated
- Conclude results of division algorithm
Single and double precision floating point extension - RV64F & RV64D
- Normalized scientific notation of decimal and binary number
- Introduction and need of IEEE754 floating point standard
- Sorting problem with existing floating point representation
- Biased floating point representation
- Floating-point standard conclusion
RV64F and RV64D floating point addition
- Decimal floating-point addition algorithm development
- Binary floating-point addition and significance of RV64D over RV64F

Audience Profile

Anyone who wants to learn world's first Open-Source instruction set architecture RISC-V
Anyone who wants to learn how to write specifications for RTL coding
Anyone looking forward to implement their own processor using all open-source tools

Prerequisites

You should have completed RISC-V ISA Part 1a online course
You should be familiar with boolean addition and subtraction concepts
You should be familiar with number systems

Tools Used

RISC-V GNU Compiler, is the RISC-V C and C++ cross-compiler. It supports two build modes:a generic ELF/Newlib toolchain and a more sophisticated Linux-ELF/glibc toolchain.