VSD - Signal Integrity

Overview

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. Crosstalk is the interference caused due to communication between the circuits. Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

  • To Learn Chip Design with minimal Crosstalk in the circuits.
  • To Design a Chip with minimal errors.

Objective

  • Introduction to Crosstalk
  • Crosstalk - Why and How Crosstalk occurs in a CHIP ??

    • High Routing Density
    • Dominant Lateral Capacitance
    • Introduction to Noise Margin
    • Noise Margin Voltage Parameters
    • Noise Margin Equation and Summary
    • Lower Supply Voltage
  • Glitch Examples And Factors Affecting Glitch Height

    • Basic Crosstalk Glitch Example
    • Glitch Discharge With High Drive Strength NMOS Transistor
    • Glitch Discharge With High Drive Strength PMOS Transistor
    • Factors Affecting Glitch Height - Spacing
    • Factors Affecting Glitch Height - Aggressor Drive Strength
    • Factors Affecting Glitch Height - Victim Drive Strength
    • Factors Affecting Glitch Height - Conclusion
  • Tolerable Glitch Heights and Introduction to AC Noise Margin
    • Impacts Of Glitch
    • Introduction to Safe and Unsafe Glitches
    • Tolerable Glitch Heights using DC Noise Margin
    • Tolerable Glitch Heights using DC Noise Margin Continued
    • AC Noise Margin
    • Impact of Load on Glitch Height
    • Justification of Load Impact and Conclusion
  • Timing Windows
    • Single Victim Multiple Aggressors
    • Introduction to Timing Window
    • Timing Window Formation
    • Bucketization based on Timing Windows
    • Final Glitch Calculation
  • Crosstalk Delta Delay Analysis
    • Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
    • Impact of Crosstalk Delta Delay on Clock Skew
    • Setup Timing Analysis Using Real Clocks
    • Impact of Crosstalk Delta Delay on Setup Timing
    • Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction
    • Hold Timing Analysis Using Real Clocks
    • Impact of Crosstalk Delta Delay on Hold Timing
  • Noise Protection Technique
    • Shielding
    • Spacing
    • Drive Strength
  • Power Supply Noise And Power Mesh Solution
    • Introduction To Power Supply Noise
    • Need of Decoupling Capacitors (DECAPS)
    • Power Supply Noise With Multiple Instantiations
    • Voltage Droop And Ground Bounce
    • Power Mesh Solution
  • Summary
  • Quiz and Evaluation

Audience Profile

  • VLSI Engineers keen to Learn Backend of Chip Design
  • Physical Design Engineer
  • Students Learning VLSI Engineering

Prerequisites

  • Basic of VLSI and Chip Design

Tools Used

NA

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